The Rambus VESA® Display Stream Compression (DSC) decoder IP core for AMD Xilinx FPGAs deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.

Download the brief to:

  • Learn the features and specifications
  • Review the block diagram
  • Check the available support and integration services

Fill out the form to receive your copy of the VESA DSC 1.2b Decoder for AMD Xilinx FPGAs product brief