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System Level Design Considerations for PCIe 6.0

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PCIe 6.0 offers many new and exciting features including a 64 GT/s data rate, PAM4 signaling, forward error correction, and a low power L0p mode. In this presentation, Lou Ternullo will walk you through all the system design considerations you will need to know before getting started on your PCIe 6.0 design, including how to get the most out of each of the PCIe devices.

Featured Speaker

Lou Ternullo

Senior Director of Product Marketing, Rambus

Lou Ternullo is senior director of product marketing for Rambus CXL and PCIe controller IP. Lou has over 30 years of semiconductor industry experience during which he has held positions in memory design and engineering, with the past 16 years focused on product management/marketing and business development in IP and ASIC-related businesses. Prior to joining Rambus, he held leadership positions at Virage Logic, Cadence and eSilicon. Lou’s technology and product-related experience includes memory, high-speed memory and storage interface IP, as well as CXL and PCIe interface IP. In his most recent roles, Lou has leveraged his experience in IP and ASIC businesses to drive product definition and execution of complete products that enable customer success.