The Rambus PCI Express® (PCIe) 5.0 interface is optimized for power and efficiency delivering maximum performance for applications in AI, 5G, Edge, Data Center and Graphics.

The interface subsystem is a low-power, area-optimized, silicon IP designed with a system-oriented approach to maximize flexibility and ease of integration. It consists of a co-verified PHY and digital controller providing a complete PCIe 5.0 SerDes subsystem.

Download this brief to:

  • Learn about the PCIe 5.0 interface subsystem
  • Review the functional block diagram
  • Review the subsystem features

PCIe 5.0 SerDes Interface Brief Cover