The latest generation of the PCI Express, PCIe 5.0, advances performance to 32 GT/s in support of advanced applications including 400G Ethernet. In this webinar, Rambus technology experts Phani Paladugu and Vinitha Seevaratnam discuss the selection and implementation considerations for PCI Express solutions. The silicon-proven Rambus PCIe 5.0 interface solution consisting of integrated PHY and memory controller is covered.
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Phani Paladugu is Director of Field Application Engineering at Rambus, responsible for interface and memory IP cores. Before joining Rambus, Phani was a Senior Manager, Interface IP applications at Cadence. Prior to this role, he spent more than 10 years at Aricent, ST Microelectronics and has extensive experience in designing high speed interfaces for ethernet, storage, networking and automotive applications. Phani holds a MS in Electrical Engineering from National Institute of Technology, Warangal, India.
Vinitha Seevaratnam is the Sr. Product Marketing Manager at Rambus, an IP Core provider specializing in Memory, PCI Express and MIPI controller cores. Vinitha’s primary focus during her 20+ year career has been in semiconductor and communication/storage product segments. Her 14+ years has been with Rambus (formerly Northwest Logic). Prior to Rambus, Vinitha worked at Northwest Logic, Thomson Grass Valley, Tektronix, Inc., and Mentor Graphics. She has a B.S. from University of Washington in Electrical Engineering.
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