Part of a full suite of memory controller add-on cores, the In-Line Error Correction Coding (In-Line ECC) core works with the Northwest Logic GDDR6 and LPDDR4 Controller cores. The In-Line ECC implements the standard Hamming Code-based DRAM Single Error Correction (SEC) and Double Error Detection (DED) algorithm.
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- How the In-Line ECC core protects transmitted data
- Features of the In-Line ECC core
- Deliverables supplied with the core