HBM3 is a high-performance memory that delivers exceptional bandwidth at reduced power and in a compact footprint. It utilizes 3D memory and a 2.5D architecture with a wide interface to deliver high throughput at a high bandwidth-per-watt efficiency for AI/ML and HPC applications.

The Rambus HBM3 Memory Subsystem supports data rates up to 8.4 Gbps per data pin. The subsystem features 16 independent channels, each containing 64 bits for a total data width of 1024 bits. The resulting bandwidth is 1075.2 GB/s per stack, with the stack consisting of 2, 4, 8, 12 or 16 DRAMs. The Rambus HBM3 Memory Subsystem comprises an HBM3 PHY and Controller for maximum performance and ease of SoC integration.

Download this brief to:

  • Review the HBM3 Memory Subsystem block diagram
  • Learn the HBM3 Memory Subsystem features
  • See the offered deliverables

Download the HBM3 Memory Subsystem Solution Brief