HBM is a high-performance memory that delivers exceptional bandwidth at reduced power and in a compact footprint. It utilizes 2.5D packaging with a wide interface and relatively low clock speed to deliver high throughput at a high bandwidth-per-watt efficiency for AI/ML and HPC applications.

The Rambus HBM2E PHY is fully compliant with the JEDEC JESD235B standard. It supports data rates up to 3.6 Gbps per data pin. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits. The resulting bandwidth is 461 GB/s per stack, with the stack consisting of 2, 4, 8 or 12 DRAMs. Together with the Northwest Logic HBM2E Controller it comprises a complete HBM2E memory interface subsystem.

Download this brief to:

  • Learn about the Rambus HBM2E PHY solution
  • See the specs and features of the HBM2E PHY

Download the Rambus HBM2 PHY Product Brief