HBM is a high-performance memory that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for high-performance computing applications.

The Rambus HBM Gen2 PHY is fully compliant to the JEDEC HBM2 standard and supports data rates up to 2 Gbps per data pin, resulting in a total bandwidth of 256 GB/s. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits, and support for a stack height of 2, 4 or 8 DRAMs. Together with the Northwest Logic HBM2 Controller it comprises a complete HBM2 memory interface subsystem.

Download this brief to:

  • Learn about the Rambus HBM2
  • See the specs and features of the HBM2

Download the Rambus HBM2 PHY Product Brief