An exponential rise in data volume, and the rapid increase of advanced workloads like AI/ML training, requires constant innovation in all aspects of computing. Yet given the broad infrastructure implications, main memory technology changes infrequently, once every 6 or 7 years. The transition to DDR5 is a watershed industry event as it will be the main memory solution in servers for the rest of this decade.
Vice President of Product Marketing, Memory Interface Chips, Rambus
John C. Eble received his B.Cmp.E. (’93), M.S.E.E (’94), and Ph.D. EE (’99) from Georgia Tech. From 1998 to 2001 he worked at Compaq on EV7 high-speed I/O circuits in the Alpha Microprocessor Development Group. He then joined Velio Communications as a circuit designer. In 2003, he joined Rambus Inc. where he has held many engineering and research management roles and specialized in the design of high-speed I/O and next-generation memory interconnect architectures. He has authored over 30 technical publications, 10 patents, and a book chapter. He is currently VP of Product Marketing for Rambus’ memory interconnect chip business unit.