Ed Sperling, Editor in Chief of Semiconductor Engineering moderates a far-ranging roundtable on the future of data center development. IDC research vice president, Shane Rau, discusses the macro trends and their impact on compute and network device architectures. Technology leaders from across Rambus will share the chip and IP solutions that can take data center performance and security to the next level.
Ed Sperling is the editor in chief of Semiconductor Engineering. He is a technology industry veteran and frequent moderator and speaker in Silicon Valley. Sperling is a former contributing editor at Forbes, and former editor in chief of Electronic News and Electronic Business. Prior to that he held top editorial positions at Ziff-Davis and CMP Publications.
Shane Rau leads IDC's computing semiconductor research within IDC's Enabling Technologies team. Mr. Rau's research covers microprocessors and SoCs, discrete graphics processors (GPUs), FPGAs, and artificial intelligence (AI) accelerators in systems across the internet, including in the data center, in PCs, and at the edge, such as embedded and intelligent systems.
Mr. Rau provides in-depth insight and intelligence on market sizing, forecasting, technology trends, vendors, pricing trends, and market share. Through collaboration with PC, server and embedded systems analysts colleagues, Mr. Rau spearheads IDC research initiatives into system supply chains, technologies and interface attach rates, as well as into the changing semiconductor vendor market power dynamics.
Neeraj is currently the VP and GM at Rambus Security BU, based out of Silicon Valley, CA. He has 20+ years of semiconductors engineering experience in compute and security domains. At Rambus, Neeraj is responsible for the CryptoManager Secure Silicon IP and Provisioning products. Before joining Rambus, Neeraj founded Kryptos Solutions, where he built an ultra-secure endpoint platform for high-risk government applications. Prior to that, Neeraj was the VP of Engineering at NXP Semiconductors, responsible for major OEM design-win for NXP’s NFC based secure payment platform. Neeraj also held various engineering positions at IBM and Intel working on gaming processors, and CPU products.
Neeraj graduated with a Master of Technology degree in Solid State Materials from the Indian Institute of Technology in Delhi, India. He attended the Stanford Executive Program at Stanford University, California.
John C. Eble received his B.Cmp.E. (’93), M.S.E.E (’94), and Ph.D. EE (’99) from Georgia Tech. From 1998 to 2001 he worked at Compaq on EV7 high-speed I/O circuits in the Alpha Microprocessor Development Group. He then joined Velio Communications as a circuit designer. In 2003, he joined Rambus Inc. where he has held many engineering and research management roles and specialized in the design of high-speed I/O and next-generation memory interconnect architectures. He has authored over 30 technical publications, 10 patents, and a book chapter. He is currently VP of Product Marketing for Rambus’ memory interconnect chip business unit.
Matt Jones is the General Manager for the IP Cores Business Unit at Rambus. He is responsible for development and growth of the company’s interface IP products, driving memory and interconnect architectural innovation in Data Center and Edge Connectivity applications. Before joining Rambus, Matt held various product line management and marketing positions for microprocessor, connectivity and power management products over a twenty-four-year career at IDT, later acquired by Renesas. Matt holds a Bachelor of Science in Electrical Engineering and a Bachelor of Arts in Economics from Stanford University.
Copyright © Rambus.com. All Rights Reserved. Privacy Policy | Trademark & Guidelines