The Rambus Compute Express Link (CXL) 3.1 Controller with AXI leverages a silicon-proven PCIe controller architecture for the path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. This controller offers support of the AMBA AXI protocol specification for traffic, and either the Intel CPI or AMBA AXI protocol specification for CXL.mem, and Intel CPI for CXL.cache.

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  • Review the block diagram
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CXL 3.1 Controller with AXI Product Brief