The PLDA Compute Express Link (CXL) 2.0 Controller leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard.

Download this brief to:

  • Learn the features and specifications
  • Review the block diagram
  • Check the integration options with the Rambus CXL/PCIe 5.0 PHY

CXL 2.0 Controller Product Brief