The PLDA Compute Express Link (CXL) 2.0 Controller with AXI leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. This controller offers support of the AMBA AXI, CPI and AMBA CXS-B protocol specifications.
Download this brief to:
- Learn the features and specifications
- Review the block diagram
- Check the integration options with the Rambus CXL/PCIe 5.0 PHY