Modern processors are incredibly complex and getting more so with each new generation. In the race to be the fastest, processor architects have added greater functionality and complexity to their designs to deliver higher levels of performance. But complexity is the enemy of security. Unanticipated interactions between components open security vulnerabilities, and as the number of components increase, those interactions rise at an exponential rate. Given this reality, the challenge of optimizing processors for both performance and security becomes insurmountable.

System designers have to get everything right while attackers need only find a single vulnerability to succeed. The announcement last year of the Meltdown, Spectre, and Foreshadow vulnerabilities, and others, raised awareness of this problem. As with many problems, “keeping it simple” can be the key to the solution. By partitioning those tasks requiring security from general purpose tasks, and processing them through a physically siloed and far simpler secure co-processor, the main processor can be optimized for performance while overall chip operations remain secure.

This webinar will answer the following questions:

  • How does inherent complexity lead to greater security vulnerabilities?
  • What are some of the threats facing SoC and processor designers?
  • How can SoCs be architected for both performance and security?
  • How can Rambus help SoC designers secure their solutions? 

Complete the form to watch the webinar.


View more in the Secure Silicon IP Series:

Part Two: Will the Real Root of Trust Please Stand Up?
Part Three: When One is Not Enough: Multiple Roots of Trust