Accelerating Data Interconnects with PCI Express 6.0 Interface IP

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The latest generation of PCI Express® (PCIe®) 6.0, advances performance to 64 GT/s in support of advanced data center workloads and networking. In this presentation, interface technology expert Lou Ternullo will discuss the new features implemented in PCIe 6.0, such as PAM4 signaling and low-latency forward error correction (FEC). He will also show how the Rambus PCIe interface IP can support your future design requirements.


Lou Ternullo

Lou Ternullo

Senior Director of Product Marketing, Interface IP, Rambus

Lou Ternullo is senior director of product marketing for Rambus CXL and PCIe controller IP. Lou has over 30 years of semiconductor industry experience during which he has held positions in memory design and engineering, with the past 16 years focused on product management/marketing and business development in IP and ASIC-related businesses. Prior to joining Rambus, he held leadership positions at Virage Logic, Cadence and eSilicon. Lou’s technology and product-related experience includes memory, high-speed memory and storage interface IP, as well as CXL and PCIe interface IP. In his most recent roles, Lou has leveraged his experience in IP and ASIC businesses to drive product definition and execution of complete products that enable customer success.