Accelerating AI Workloads with Composable Memory & Hardware Acceleration

The increasing demand for AI and machine learning applications drives the need for high-performance, low-latency memory solutions. This session presents a novel approach to integrating composable memory solutions with AI and caching services. By leveraging Rambus CXL IP and ZeroPoint hardware-accelerated compression IP in a fully assembled controller prototype FPGA system, significant performance improvements can be realized for real-world workloads such as Meta Cachelib, a widely used hyperscale caching application for AI services. 

Join Lou Ternullo from Rambus along with Yiannis Nikolakopoulos from ZeroPoint as they discuss a solution that addresses the evolving requirements of hyperscale data centers, as outlined in open compute specifications. Combining the flexibility of CXL with the efficiency of hardware acceleration can achieve efficient data movement, compression, and decompression, and reduced system latency and power consumption. Detailed performance benchmarks and analysis will be presented highlighting the benefits of this approach in terms of throughput, latency, and energy efficiency.

Featured Speakers

Yiannis Nikolakopoulos

Software Lead, ZeroPoint Technologies

Yiannis leads the Software Team at ZeroPoint Technologies, he has deep experience in Hardware/Software co-design, taking ideas from research to prototyping all the way to production. He is an expert in the areas of memory management, Linux kernel and concurrency. 

Lou Ternullo

Senior Director of Product Marketing of CXL and PCIe Controller IP, Rambus

Lou has over 30 years of semiconductor industry experience during which he has held positions in memory design and engineering, with the past 16 years focused on product management/marketing and business development in IP and ASIC-related businesses. Prior to joining Rambus, he held leadership positions at Virage Logic, Cadence and eSilicon. Lou’s technology and product-related experience includes memory, high-speed memory and storage interface IP, as well as CXL and PCIe interface IP. In his most recent roles, Lou has leveraged his experience in IP and ASIC businesses to drive product definition and execution of complete products that enable customer success. 